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Freescale Semiconductor /MK70F15WS /PTA /PDIR

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Interpret as PDIR

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https://regviz.com/r/Freescale Semiconductor/MK61F15WS/PTD/PDIR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PDI

PDI=0

Description

Port Data Input Register

Fields

PDI

Port Data Input

0 (0): Pin logic level is logic 0 or, is not configured for use by digital function.

1 (1): Pin logic level is logic 1.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data